When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
External Interrupt Request 2 Enable
When the INT2 bit is set and the I-bit in the Status Register
(SREG) is set, the external pin interrupt is enabled. The Interrupt Sense Control2
bits 1/0 (ISC21 and ISC20) in the External Interrupt Control Register A (EICRA)
define whether the external interrupt is activated on rising and/or falling edge of
the INT2 pin or level sensed. Activity on the pin will cause an interrupt request
even if INT2 is configured as an output. The corresponding interrupt of External
Interrupt Request 2 is executed from the INT2 Interrupt
Vector.
External Interrupt Request 1 Enable
When the INT1 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
External Interrupt
Request 0 Enable
When the INT0 bit is
set and the I-bit in the Status Register (SREG) is set, the external pin interrupt
is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0
Interrupt Vector.