The Port B pins with alternate functions
are shown in the table below:
Table 1. Port B Pins Alternate
Functions| Port
Pin |
Alternate
Functions |
|---|
| PB7 |
SCK0 (SPI0 Bus Master clock input)
OC3B (Timer/Counter 3 Output Compare Match B Output)
OC4B (Timer/Counter 4 Output Compare Match B Output)
PCINT15 (Pin Change Interrupt 15)
|
| PB6 |
MISO0 (SPI0 Bus Master Input/Slave Output)
OC3A (Timer/Counter 3 Output Compare Match A Output)
PCINT14 (Pin Change Interrupt 14)
|
| PB5 |
MOSI0 (SPI0 Bus Master Output/Slave Input)
ICP3 (Timer/Counter3 Input Capture Trigger)
PCINT13 (Pin Change Interrupt 13)
|
| PB4 |
SS0 (SPI0 Slave Select input)
OC0B (Timer/Counter 0 Output Compare Match B Output)
PCINT12 (Pin Change Interrupt 12)
|
| PB3 |
AIN1 (Analog Comparator Negative Input)
OC0A (Timer/Counter 0 Output Compare Match A Output)
PCINT11 (Pin Change Interrupt 11)
|
| PB2 |
AIN0 (Analog Comparator Positive Input)
INT2 (External Interrupt 2 Input)
PCINT10 (Pin Change Interrupt 10)
|
| PB1 |
T1 (Timer/Counter 1 External Counter Input)
CLKO (Divided System Clock Output)
PCINT9 (Pin Change Interrupt 9)
|
| PB0 |
T0 (Timer/Counter 0 External Counter Input)
XCK0 (USART0 External Clock Input/Output)
PCINT8 (Pin Change Interrupt 8)
|
The alternate pin configuration is as
follows:
- SCK0/OC3B/OC4B/PCINT15 – Port B, Bit
7
- SCK0: Master Clock output,
Slave Clock input pin for SPI0 channel. When the SPI0 is enabled as a slave,
this pin is configured as an input regardless of the setting of DDRB7. When the
SPI0 is enabled as a master, the data direction of this pin is controlled by
DDRB7. When the pin is forced to be an input, the pull-up can still be
controlled by the PORTB7 bit.
- OC3B: Output Compare Match B
output. The PB7 pin can serve as an external output for the Timer/Counter3
Output Compare. The pin has to be configured as an output (DDRB7 set “1”) to
serve this function. The OC3B pin is also the output pin for the PWM mode timer
function.
- OC4B: Output Compare Match B
output. The PB7 pin can serve as an external output for the Timer/Counter4
Output Compare. The pin has to be configured as an output (DDRB7 set “1”) to
serve this function. The OC4B pin is also the output pin for the PWM mode timer
function.
- PCINT15: Pin Change Interrupt
source 15. The PB7 pin can serve as an external interrupt source.
- MISO0/OC3A/PCINT14 – Port B, Bit 6
- MISO0: Master Data input, Slave
Data output pin for SPI0 channel. When the SPI0 is enabled as a master, this
pin is configured as an input regardless of the setting of DDRB6. When the SPI0
is enabled as a slave, the data direction of this pin is controlled by DDRB6.
When the pin is forced to be an input, the pull-up can still be controlled by
the PORTB6 bit.
- OC3A: Output Compare Match A
output. The PB6 pin can serve as an external output for the Timer/Counter3
Output Compare. The pin has to be configured as an output (DDRB6 set “1”) to
serve this function. The OC3A pin is also the output pin for the PWM mode timer
function.
- PCINT14: Pin Change Interrupt
source 14. The PB6 pin can serve as an external interrupt source.
- MOSI0/ICP3/PCINT13 – Port B, Bit 5
- MOSI0: SPI0 Master Data output,
Slave Data input for SPI0 channel. When the SPI0 is enabled as a slave, this
pin is configured as an input regardless of the setting of DDRB5. When the SPI0
is enabled as a master, the data direction of this pin is controlled by DDRB5.
When the pin is forced to be an input, the pull-up can still be controlled by
the PORTB5 bit.
- ICP3: Input Capture Pin 3. The
PB5 pin can act as an input capture pin for Timer/Counter3.
- PCINT13: Pin Change Interrupt
source 13. The PB5 pin can serve as an external interrupt source.
- SS0/OC0B/PCINT12 – Port B, Bit 4
- SS0:
Slave Port Select input. When the SPI0 is enabled as a slave, this pin is
configured as an input regardless of the setting of DDRB4. As a slave, the SPI0
is activated when this pin is driven low. When the SPI0 is enabled as a master,
the data direction of this pin is controlled by DDRB4. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB4 bit.
- OC0B: Output Compare Match B
output. The PB4 pin can serve as an external output for the Timer/Counter0
Output Compare. The pin has to be configured as an output (DDRB4 set “1”) to
serve this function. The OC0B pin is also the output pin for the PWM mode timer
function.
- PCINT12: Pin Change Interrupt source 12. The PB4 pin can serve as an external
interrupt source.
- AIN1/OC0A/PCINT11– Port B, Bit 3
- AIN1: Analog Comparator
Negative input. This pin is directly connected to the negative input of the
Analog Comparator.
- OC0A: Output Compare Match A
output. The PB3 pin can serve as an external output for the Timer/Counter0
Output Compare. The pin has to be configured as an output (DDRB3 set “1”) to
serve this function. The OC0A pin is also the output pin for the PWM mode timer
function.
- PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external
interrupt source.
- AIN0/INT2/PCINT10 – Port B, Bit 2
- AIN0: Analog Comparator Positive input. This pin is directly connected to the
positive input of the Analog Comparator.
- INT2: External Interrupt source 2. The PB2 pin can serve as an External
Interrupt source to the MCU.
- PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external
interrupt source.
- T1/CLKO/PCINT9 – Port B, Bit 1
- T1: Timer/Counter1 counter source.
- CLKO: Divided System Clock: The
divided system clock can be output on the PB1 pin. The divided system clock
will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and
DDRB1 settings. It will also be output during reset.
- PCINT9: Pin Change Interrupt source 9: The PB1 pin can serve as an external
interrupt source.
- T0/XCK0/PCINT8 – Port B, Bit 0
- T0: Timer/Counter0 counter source.
- XCK0: USART0 External clock.
The Data Direction Register (DDRB0) controls whether the clock is output (DDRB0
set “1”) or input (DDRB0 cleared). The XCK0 pin is active only when the USART0
operates in Synchronous mode.
- PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external
interrupt source.
Table 2 and Table 3 relate the alternate functions of Port B to the overriding signals shown
in Figure 1. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO
signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 2. Overriding Signals for Alternate
Functions in PB7...PB4| Signal
Name |
PB7/SCK0/OC3B/OC4B/PCINT15 |
PB6/MISO0/OC3A/PCINT14 |
PB5/MOSI0/ICP3/PCINT13 |
PB4/SS0/OC0B/PCINT12 |
|---|
| PUOE |
SPE0 •
MSTR |
SPE0 •
MSTR |
SPE0 •
MSTR |
SPE0 •
MSTR |
| PUOV |
PORTB7 •
PUD |
PORTB6 •
PUD |
PORTB5 •
PUD |
PORTB4 •
PUD |
| DDOE |
SPE0 •
MSTR |
SPE0 •
MSTR |
SPE0 •
MSTR |
SPE0 •
MSTR |
| DDOV |
0 |
0 |
0 |
0 |
| PVOE |
SPE0 • MSTR
OC3B/OC4B ENABLE
|
SPE0 • MSTR
OC3A ENABLE
|
SPE0 •
MSTR |
OC0B
ENABLE |
| PVOV |
SCK0 OUTPUT +
OC3B/OC4B |
SPI0 SLAVE
OUTPUT + OC3A |
SPI0 MSTR
OUTPUT |
OC0B |
| DIEOE |
PCINT15 •
PCIE1 |
PCINT14 •
PCIE1 |
PCINT13 •
PCIE1 |
PCINT12 •
PCIE1 |
| DIEOV |
1 |
1 |
1 |
1 |
| DI |
SCK0 INPUT
PCINT15 INPUT
|
SPI0 MSTR INPUT
PCINT14 INPUT
|
SPI0 SLAVE INPUT
ICP3 INPUT
PCINT13 INPUT
|
SPI SS0
PCINT12 INPUT
|
| AIO |
- |
- |
– |
– |
Table 3. Overriding Signals for Alternate
Functions in PB3...PB0| Signal
Name |
PB3/AIN1/OC0A/PCINT11 |
PB2/AIN0/INT2/PCINT10 |
PB1/T1/CLKO/PCINT9 |
PB0/T0/XCK0/PCINT8 |
|---|
| PUOE |
0 |
0 |
0 |
0 |
| PUOV |
0 |
0 |
0 |
0 |
| DDOE |
0 |
0 |
CKOUT |
0 |
| DDOV |
0 |
0 |
CKOUT |
0 |
| PVOE |
OC0A
ENABLE |
0 |
CKOUT |
UMSEL |
| PVOV |
OC0A |
0 |
CLK
I/O |
XCK0
OUTPUT |
| DIEOE |
PCINT11 •
PCIE1 |
INT2 ENABLE
PCINT10 • PCIE1
|
PCINT9 •
PCIE1 |
PCINT8 •
PCIE1 |
| DIEOV |
1 |
1 |
1 |
1 |
| DI |
PCINT11
INPUT
|
INT2 INPUT
PCINT10 INPUT
|
T1 INPUT
PCINT9 INPUT
|
T0 INPUT
XCK0 INPUT
PCINT8 INPUT
|
| AIO |
AIN1
INPUT |
AIN0
INPUT |
– |
– |