Pin Change Interrupt Control Register
Name:
PCICR
Offset:
0x68
Reset:
0x00
Access:
-
Bit76543210
PCIE4PCIE3PCIE2PCIE1PCIE0
AccessR/WR/WR/WR/WR/W
Reset00000

Bit 4 – PCIE4: Pin Change Interrupt Enable 4

Pin Change Interrupt Enable 4

When the PCIE4 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 4 is enabled. Any change on any enabled PCINT[39:32] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI4 Interrupt Vector. PCINT[39:32] pins are enabled individually by the PCMSK4 Register.

Bit 3 – PCIE3: Pin Change Interrupt Enable 3

Pin Change Interrupt Enable 3

When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3 Interrupt Vector. PCINT[31:24] pins are enabled individually by the PCMSK3 Register.

Bit 2 – PCIE2: Pin Change Interrupt Enable 2

Pin Change Interrupt Enable 2

When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins are enabled individually by the PCMSK2 Register.

Bit 1 – PCIE1: Pin Change Interrupt Enable 1

Pin Change Interrupt Enable 1

When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled individually by the PCMSK1 Register.

Bit 0 – PCIE0: Pin Change Interrupt Enable 0

Pin Change Interrupt Enable 0

When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.