When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRD/OCDR7 | OCDR 6 | OCDR 5 | OCDR 4 | OCDR 3 | OCDR 2 | OCDR 1 | OCDR 0 |
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
USART Receive Complete
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
On-chip Debug Register