RX Complete
Interrupt Enable
Writing this bit to
one enables interrupt on the UCSRnA.RXC Flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag
in SREG is written to one and the RXC bit in UCSRnA is set.
TX Complete
Interrupt Enable
Writing this bit to
one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be
generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG
is written to one and the TXC bit in UCSRnA is set.
USART Data Register
Empty Interrupt Enable
Writing this bit to
one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be
generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG
is written to one and the UDRE bit in UCSRnA is set.
Receiver
Enable
Writing this bit to
one enables the USART Receiver. The Receiver will override normal port operation for
the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FE, DOR, and UPE Flags.
Transmitter
Enable
Writing this bit to
one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing
TXEN to zero) will not become effective until ongoing and pending transmissions are
completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do
not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxDn port.
Character Size
The UCSZ2 bits combined with the UCSZ[1:0] bit in UCSRnC sets the
number of data bits (Character Size) in a frame the Receiver and Transmitter
use.
This bit is reserved in Master SPI Mode (MSPIM).
Receive Data Bit
8
RXB8 is the ninth data bit of the received character when operating
with serial frames with nine data bits. Must be read before reading the low bits
from UDRn.
This bit is reserved in Master SPI Mode (MSPIM).
Transmit Data Bit
8
TXB8 is the ninth data bit in the character to be transmitted when
operating with serial frames with nine data bits. Must be written before writing
the low bits to UDRn.
This bit is reserved in Master SPI Mode (MSPIM).