TIMSK – Timer/Counter Interrupt Mask Register

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

Name:
TIMSK
Offset:
0x39 [ID-00000d14]
Reset:
0x00
Access:
When addressing I/O Registers as data space the offset address is 0x59
Bit76543210
OCIE2TOIE2
AccessR/WR/W
Reset00

Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

Timer/Counter

2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).

Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

Timer/Counter

2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).