TCCR2 – Timer/Counter Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FOC2 | WGM20 | COM2n[1:0] | WGM21 | CS2n[2:0] | |||
AccessW | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP.
The FOC2 bit is always read as zero.
Waveform Generation Mode [n=0:1]
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See table below and Modes of Operation.
Mode | WGM21 (CTC2) | WGM20 (PWM2) | Timer/Counter Mode of Operation(1) | TOP | Update of OCR2 | TOV2 Flag Set |
---|---|---|---|---|---|---|
0 | 0 | 0 | Normal | 0xFF | Immediate | MAX |
1 | 0 | 1 | PWM, Phase Correct | 0xFF | TOP | BOTTOM |
2 | 1 | 0 | CTC | OCR2 | Immediate | MAX |
3 | 1 | 1 | Fast PWM | 0xFF | BOTTOM | MAX |
Compare Match Output Mode [n = 1:0]
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. The following table shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM).
COM21 | COM20 | Description |
---|---|---|
0 | 0 | Normal port operation, OC2 disconnected. |
0 | 1 | Toggle OC2 on Compare Match |
1 | 0 | Clear OC2 on Compare Match |
1 | 1 | Set OC2 on Compare Match |
The next table shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
COM21 | COM20 | Description |
---|---|---|
0 | 0 | Normal port operation, OC2 disconnected. |
0 | 1 | Reserved |
1 | 0 | Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) |
1 | 1 | Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode) |
The table below shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode.
COM21 | COM20 | Description |
---|---|---|
0 | 0 | Normal port operation, OC2 disconnected. |
0 | 1 | Reserved |
1 | 0 | Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. |
1 | 1 | Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. |
Waveform Generation Mode [n=0:1]
Refer to WGM20.
Clock Select [n = 2:0]
The three Clock Select bits select the clock source to be used by the Timer/Counter.
CS22 | CS21 | CS20 | Description |
---|---|---|---|
0 | 0 | 0 | No clock source (Timer/Counter stopped). |
0 | 0 | 1 | clkI/O/1 (No prescaling) |
0 | 1 | 0 | clkI/O/8 (From prescaler) |
0 | 1 | 1 | clkI/O/32 (From prescaler) |
1 | 0 | 0 | clkI/O/64 (From prescaler) |
1 | 0 | 1 | clkI/O/128 (From prescaler) |
1 | 1 | 0 | clkI/O/256 (From prescaler) |
1 | 1 | 1 | clkI/O/1024 (From prescaler) |