Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to the block diagram above.
The USART Baud Rate Register (UBRR) and the downcounter connected to it function as a programmable prescaler or baud rate generator. The downcounter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits.
The table below contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source.
Operating Mode  Equation for Calculating Baud Rate^{(1)}  Equation for Calculating UBRR Value 

Asynchronous Normal mode (U2X = 0) 


Asynchronous Double Speed mode (U2X = 1) 


Synchronous Master mode 


Some examples of UBRR values for some system clock frequencies are found in Table 1.