The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
The following figure is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented.
Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows:
The following table lists assembly and C implementation examples. Note that the code below assumes that several definitions have been made, e.g. by using include-files.
Assembly Code Example | C Example | Comments | |
---|---|---|---|
1 |
ldi r16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN) out TWCR, r16 |
TWCR = (1<<TWINT)|(1<<TWSTA)|(1<<TWEN) |
Send START condition |
2 |
wait1: in r16,TWCR sbrs r16,TWINT rjmp wait1 |
while (!(TWCR & (1<<TWINT)));
|
Wait for TWINT Flag set. This indicates that the START condition has been transmitted. |
3 |
in r16,TWSR andi r16, 0xF8 cpi r16, START brne ERROR |
if ((TWSR & 0xF8) != START)
ERROR();
|
Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR. |
ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 |
TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); |
Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address. | |
4 |
wait2: in r16,TWCR sbrs r16,TWINT rjmp wait2 |
while (!(TWCR & (1<<TWINT)));
|
Wait for TWINT Flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received. |
5 |
in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR |
if ((TWSR & 0xF8) != MT_SLA_ACK)
ERROR();
|
Check value of TWI Status Register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR. |
ldi r16, DATA out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 |
TWDR = DATA; TWCR = (1<<TWINT) | (1<<TWEN); |
Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data. | |
6 |
wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3 |
while (!(TWCR & (1<<TWINT)));
|
Wait for TWINT Flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received. |
7 |
in r16,TWSR andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR |
if ((TWSR & 0xF8) != MT_DATA_ACK)
ERROR();
|
Check value of TWI Status Register. Mask prescaler bits. If status different from MT_DATA_ACK go to ERROR. |
ldi r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) out TWCR, r16 |
TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWSTO); |
Transmit STOP condition. |