TWAR – TWI (Slave) Address Register

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated.

Name:
TWAR
Offset:
0x02
Reset:
0x01
Access:
When addressing I/O Registers as data space the offset address is 0x22
Bit76543210
TWAn[6:0]TWGCE
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000010

Bits 7:1 – TWAn: TWI (Slave) Address [n = 6:0]

TWI (Slave) Address [n = 6:0]

These seven bits constitute the slave address of the TWI unit.

Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.