The USART is fully compatible with the AVR UART regarding:
- Bit locations inside all USART Registers.
- Baud Rate Generation.
- Transmitter Operation.
- Transmit Buffer Functionality.
- Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in
some special cases:
- A second Buffer Register has been added. The two Buffer Registers operate as a
circular FIFO buffer. Therefore the UDR must only be read once for each incoming
data! More important is the fact that the Error Flags (FE and DOR) and the ninth
data bit (RXB8) are buffered with the data in the receive buffer. Therefore the
status bits must always be read before the UDR Register is read. Otherwise the error
status will be lost since the buffer state is lost.
- The Receiver Shift Register can now
act as a third buffer level. This is done by allowing the received data to remain in
the serial Shift Register (see Block Diagram in previous section) if the Buffer
Registers are full, until a new start bit is detected. The USART is therefore more
resistant to Data OverRun (DOR) error conditions.
The following control bits have changed name, but have same functionality and register
location:
- CHR9 is changed to UCSZ2.
- OR is changed to DOR.