I/O Multiplexing

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions.

The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 1. 32-Pin TQFP and MLF: PORT Function Multiplexing
No PAD32 EXTINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI
1 PD[3] INT1  
2 PD[4] T0 XCK0
3 GND      
4 VCC
5 GND
6 VCC    
7 PB[6] XTAL1/TOSC1
8 PB[7] XTAL2/TOSC2
9 PD[5]   T1
10 PD[6] AIN0  
11 PD[7] AIN1
12 PB[0]   ICP1
13 PB[1] OC1A
14 PB[2] OC1B SS0
15 PB[3] OC2   MOSI0
16 PB[4]   MISO0
17 PB[5]   SCK0
18 AVCC
19 ADC6 ADC6    
20 AREF
21 GND
22 ADC7 ADC7    
23 PC[0] ADC0  
24 PC[1] ADC1  
25 PC[2] ADC2
26 PC[3] ADC3
27 PC[4] ADC4 SDA0
28 PC[5] ADC5 SCL0
29 PC[6]/RESET
30 PD[0]   RXD0
31 PD[1]   TXD0
32 PD[2] INT0    
Table 2. 28-Pin PDIP: PORT Function Multiplexing
No PAD28 EXTINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI
1 PC[6]/RESET    
2 PD[0]   RXD0
3 PD[1]     TXD0  
4 PD[2] INT0
5 PD[3] INT1
6 PD[4] T0   XCK0  
7 VCC  
8 GND  
9 PB[6] XTAL1/TOSC1    
10 PB[7]   XTAL2/TOSC2  
11 PD[5]   T1
12 PD[6] AIN0    
13 PD[7] AIN1  
14 PB[0] ICP1    
15 PB[1] OC1A    
16 PB[2] OC1B   SS0
17 PB[3] OC2   MOSI0
18 PB[4] MISO0
19 PB[5]     SCK0
20 AVCC
21 AREF
22 GND      
23 PC[0] ADC0  
24 PC[1] ADC1  
25 PC[2] ADC2
26 PC[3] ADC3
27 PC[4] ADC4 SDA0
28 PC[5] ADC5 SCL0