Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare flag (OCF2) at the next timer clock cycle. If enabled, (OCIE2 = 1), the Output Compare flag generates an Output Compare interrupt. The OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max. and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (refer to Modes of Operation).

The following figure shows a block diagram of the Output Compare unit.

Figure 1. Output Compare Unit, Block Diagram

The OCR2 register is double buffered when using any of the Pulse-Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, nonsymmetrical PWM pulses, thereby making the output glitch-free.

The OCR2 register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer register, and if double buffering is disabled, the CPU will access the OCR2 directly.