Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.

The SCL frequency is generated according to the following equation:

SCL frequency=CPU Clock frequency16+2(TWBR)PrescalerValue
Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See the Two-Wire Serial Interface Characteristics for a suitable value of the pull-up resistor.