Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). The next figure shows a timing diagram for the setting of OCF1x.

Figure 1. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

The next figure shows the same timing data, but with the prescaler enabled.

Figure 2. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f_{clk_I/O}/8)

The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM.

Figure 3. Timer/Counter Timing Diagram, no Prescaling.

The next figure shows the same timing data, but with the prescaler enabled.

Figure 4. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)