Slave Transmitter Mode

In the Slave Transmitter (ST) mode, a number of data bytes are transmitted to a Master Receiver, as in the figure below. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.

Figure 1. Data Transfer in Slave Transmitter Mode

To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows:

The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.TWGCI=1, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.

TWCR must hold a value of the type TWCR=0100010x - TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in the table below. The ST mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state 0xB0).

If the TWCR.TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives all '1' as serial data. State 0xC8 is entered if the Master demands additional data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting NACK from the Master).

While TWCR.TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing '1' to it). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.

Note: The 2-wire Serial Interface Data Register (TWDR) does not reflect the last byte present on the bus when waking up from these Sleep modes.
Table 1. Status Codes for Slave Transmitter Mode
Status Code

(TWSR)

Prescaler Bits are 0

Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWINT TWEA
0xA8 Own SLA+R has been received;

ACK has been returned

Load data byte or

Load data byte

X

X

0

0

1

1

0

1

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

0xB0 Arbitration lost in SLA+R/W as Master; own SLA+R has been

received; ACK has been returned

Load data byte or

Load data byte

X

X

0

0

1

1

0

1

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

0xB8 Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Load data byte

X

X

0

0

1

1

0

1

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

0xC0 Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

No TWDR action or

No TWDR action or

No TWDR action

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free

0xC8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received No TWDR action or

No TWDR action or

No TWDR action or

No TWDR action

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free

Figure 2. Formats and States in the Slave Transmitter Mode