Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode.

Below is a block diagram of the clock generation logic.

Figure 1. Clock Generation Logic, Block Diagram

Signal description:

Transmitter clock (internal signal).
Receiver base clock (internal signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (internal signal). Used for synchronous master operation.
XTAL pin frequency (System Clock).