WDTCR – Watchdog Timer Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDCE | WDE | WDPn[2:0] | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 |
Watchdog Change Enable
Watchdog Enable
Watchdog Timer Prescaler 2, 1, and 0 [n = 2:0]
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in the table below.
WDP2 | WDP1 | WDP0 | Number of WDT Oscillator Cycles | Typical Time-out at VCC = 3.0V | Typical Time-out at VCC = 5.0V | |
---|---|---|---|---|---|---|
0 | 0 | 0 | 16K (16,384) | 17.1ms | 16.3ms | |
0 | 0 | 1 | 32K (32,768) | 34.3ms | 32.5ms | |
0 | 1 | 0 | 64K (65,536) | 68.5ms | 65ms | |
0 | 1 | 1 | 128K (131,072) | 0.14s | 0.13s | |
1 | 0 | 0 | 256K (262,144) | 0.27s | 0.26s | |
1 | 0 | 1 | 512K (524,288) | 0.55s | 0.52s | |
1 | 1 | 0 | 1,024K (1,048,576) | 1.1s | 1.0s | |
1 | 1 | 1 | 2,048K (2,097,152) | 2.2s | 2.1s |