Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x3F (0x5F) SREG I T H S V N Z C
0x3E (0x5E) SPH SP10 SP9 SP8
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0x3C (0x5C) Reserved
0x3B (0x5B) GICR INT1 INT0 IVSEL IVCE
0x3A (0x5A) GIFR INTF1 INTF0
0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 TOIE0
0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 TOV0
0x37 (0x57) SPMCR SPMIE RWWSB RWWSRE BLBSET PGWRT PGERS SPMEN
0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE
0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00
0x34 (0x54) MCUCSR WDRF BORF EXTRF PORF
0x33 (0x53) TCCR0 CS02 CS01 CS00
0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits)
0x31 (0x51) OSCCAL Oscillator Calibration Register
0x30 (0x50) SFIOR ACME PUD PSR2 PSR10
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10
0x2E (0x4E) TCCR1B ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte
0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High byte
0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low byte
0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High byte
0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low byte
0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte
0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low byte
0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20
0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits)
0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register
0x22 (0x42) ASSR AS2 TCN2UB OCR2UB TCR2UB
0x21 (0x41) WDTCR WDCE WDE WDP2 WDP1 WDP0
0x20(1) (0x40)(1) UBRRH URSEL UBRR[11:8]
UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL
0x1F (0x3F) EEARH EEAR8
0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0
0x1D (0x3D) EEDR EEPROM Data Register
0x1C (0x3C) EECR EERIE EEMWE EEWE EERE
0x1B (0x3B) Reserved  
0x1A (0x3A) Reserved
0x19 (0x39) Reserved
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0
0x15 (0x35) PORTC PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0
0x14 (0x34) DDRC DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0
0x13 (0x33) PINC PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0
0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0
0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0
0x0F (0x2F) SPDR SPI Data Register
0x0E (0x2E) SPSR SPIF WCOL SPI2X
0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
0x0C (0x2C) UDR USART I/O Data Register
0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM
0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8
0x09 (0x29) UBRRL USART Baud Rate Register Low byte
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0
0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX3 MUX2 MUX1 MUX0
0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0
0x05 (0x25) ADCH ADC Data Register High byte
0x04 (0x24) ADCL ADC Data Register Low byte
0x03 (0x23) TWDR Two-wire Serial Interface Data Register
0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 TWPS1 TWPS0
0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register
Note:
  1. 1.Refer to the USART description for details on how to access UBRRH and UCSRC.
  2. 2.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
  3. 3.Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.