Instruction Set Summary

Table 1. Arithmetic and Logic Instructions
Mnemonic Operands Description   Op   Flags
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H
ADIW Rd, K Add Immediate to Word Rd + 1:Rd Rd + 1:Rd + K Z,C,N,V,S
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S
AND Rd, Rr Logical AND Rd Rd • Rr Z,N,V,S
ANDI Rd, K Logical AND with Immediate Rd Rd • K Z,N,V,S
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S
EOR Rd, Rr Exclusive OR Rd Rd ⊕ Rr Z,N,V,S
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S
CBR Rd,K Clear Bit(s) in Register Rd Rd • ($FFh - K) Z,N,V,S
INC Rd Increment Rd Rd + 1 Z,N,V,S
DEC Rd Decrement Rd Rd - 1 Z,N,V,S
TST Rd Test for Zero or Minus Rd Rd • Rd Z,N,V,S
CLR Rd Clear Register Rd Rd ⊕ Rd Z,N,V,S
SER Rd Set Register Rd $FF None
Table 2. Branch Instructions
Mnemonic Operands Description   Op   Flags
RJMP k Relative Jump PC PC + k + 1 None
IJMP   Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←


Z

0

None
RCALL k Relative Call Subroutine PC PC + k + 1 None
ICALL   Indirect Call to (Z)

PC(15:0)

PC(21:16)

←


Z

0

None
RET   Subroutine Return PC STACK None
RETI   Interrupt Return PC STACK I
CPSE Rd,Rr Compare, skip if Equal if (Rd = Rr) PC PC + 2 or 3 None
CP Rd,Rr Compare Rd - Rr     Z,C,N,V,S,H
CPC Rd,Rr Compare with Carry Rd - Rr - C     Z,C,N,V,S,H
CPI Rd,K Compare with Immediate Rd - K     Z,C,N,V,S,H
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2 or 3 None
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3 None
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC PC + k + 1 None
BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC PC + k + 1 None
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None
Table 3. Data Transfer Instructions
Mnemonic Operands Description   Op   Flags
MOV Rd, Rr Copy Register Rd Rr None
LDI Rd, K Load Immediate Rd K None
LDS Rd, k Load Direct from data space Rd (k) None
LD Rd, X Load Indirect Rd (X) None
LD Rd, X+ Load Indirect and Post-Increment

Rd

X

←


(X)


X + 1

None
LD Rd, -X Load Indirect and Pre-Decrement

X

Rd

←


X - 1


(X)

None
LD Rd, Y Load Indirect Rd (Y) None
LD Rd, Y+ Load Indirect and Post-Increment

Rd

Y

←


(Y)

Y + 1

None
LD Rd, -Y Load Indirect and Pre-Decrement

Y

Rd

←


Y - 1


(Y)

None
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None
LD Rd, Z Load Indirect Rd (Z) None
LD Rd, Z+ Load Indirect and Post-Increment

Rd

Z

←


(Z)

Z+1

None
LD Rd, -Z Load Indirect and Pre-Decrement

Z

Rd

←


Z - 1

(Z)

None
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None
STS k, Rr Store Direct to Data Space (k) Rd None
ST X, Rr Store Indirect (X) Rr None
ST X+, Rr Store Indirect and Post-Increment

(X)

X

←


Rr

X + 1

None
ST -X, Rr Store Indirect and Pre-Decrement

X

(X)

←


X - 1


Rr

None
ST Y, Rr Store Indirect (Y) Rr None
ST Y+, Rr Store Indirect and Post-Increment

(Y)

Y

←


Rr

Y + 1

None
ST -Y, Rr Store Indirect and Pre-Decrement

Y

(Y)

←


Y - 1

Rr

None
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None
ST Z, Rr Store Indirect (Z) Rr None
ST Z+, Rr Store Indirect and Post-Increment

(Z)

Z

←


Rr


Z + 1
None
ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1 None
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None
LPM   Load Program Memory R0 (Z) None
IN Rd, A In From I/O Location Rd I/O(A) None
OUT A, Rr Out To I/O Location I/O(A) Rr None
PUSH Rr Push Register on Stack STACK Rr None
POP Rd Pop Register from Stack Rd STACK None
Table 4. Bit and Bit-Test Instructions
Mnemonic Operands Description   Op   Flags
LSL Rd Logical Shift Left

Rd(n+1)

Rd(0)

C

Rd(n)


0

Rd(7)

Z,C,N,V,H
LSR Rd Logical Shift Right

Rd(n)

Rd(7)

C

Rd(n+1)


0

Rd(0)

Z,C,N,V
ROL Rd Rotate Left Through Carry

Rd(0)

Rd(n+1)

C

C

Rd(n)

Rd(7)

Z,C,N,V,H
ROR Rd Rotate Right Through Carry

Rd(7)

Rd(n)

C

C

Rd(n+1)

Rd(0)

Z,C,N,V
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None
BST Rr, b Bit Store from Register to T T Rr(b) T
BLD Rd, b Bit load from T to Register Rd(b) T None
BSET s Flag Set SREG(s) 1 SREG(s)
BCLR s Flag Clear SREG(s) 0 SREG(s)
SEC   Set Carry C 1 C
CLC   Clear Carry C 0 C
SEN   Set Negative Flag N 1 N
CLN   Clear Negative Flag N 0 N
SEZ   Set Zero Flag Z 1 Z
CLZ   Clear Zero Flag Z 0 Z
SEI   Global Interrupt Enable I 1 I
CLI   Global Interrupt Disable I 0 I
SES   Set Signed Test Flag S 1 S
CLS   Clear Signed Test Flag S 0 S
SEV   Set Two’s Complement Overflow V 1 V
CLV   Clear Two’s Complement Overflow V 0 V
SET   Set T in SREG T 1 T
CLT   Clear T in SREG T 0 T
SEH   Set Half Carry Flag in SREG H 1 H
CLH   Clear Half Carry Flag in SREG H 0 H
Table 5. MCU Control Instructions
Mnemonic Operands Description Operation Flags
BREAK   Break (See also debug interface description) None
NOP   No Operation   None
SLEEP   Sleep (See also power management and sleep description) None
WDR   Watchdog Reset (See also Watchdog Controller description) None
Note:
  1. 1.Cycle time for data memory accesses assume internal RAM access and are not valid for accesses through the NVM controller. A minimum of one extra cycle must be added when accessing memory through the NVM controller (such as Flash and EEPROM), but depending on simultaneous accesses by other masters or the NVM controller state, there may be more than one extra cycle.