The Store Program Memory Control and Status Register contains the control
bits needed to control the Boot Loader operations.
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these offset addresses.
SPM Interrupt
Enable
When the SPMIE bit
is written to one, and the I-bit in the Status Register is set (one), the SPM ready
interrupt will be enabled. The SPM ready Interrupt will be executed as long as the
SPMEN bit in the SPMCR Register is cleared.
Read-While-Write
Section Busy
When a
Self-Programming (page erase or page write) operation to the RWW section is
initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the
RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is
written to one after a Self-Programming operation is completed. Alternatively the
RWWSB bit will automatically be cleared if a page load operation is
initiated.
Read-While-Write
Section Read Enable
When programming
(Page Erase or Page Write) to the RWW section, the RWW section is blocked for
reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user
software must wait until the programming is completed (SPMEN will be cleared). Then,
if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section
cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write
(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the
Flash load operation will abort and the data loaded will be
lost.
Boot Lock Bit
Set
If this bit is written to one at the same time as SPMEN, the next
SPM instruction within four clock cycles sets Boot Lock bits, according to the
data in R0. The data in R1 and the address in the Z-pointer are ignored. The
BLBSET bit will automatically be cleared upon completion of the Lock bit set, or
if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are
set in the SPMCR Register (SPMCR.BLBSET and SPMCR.SPMEN), will read either the
Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register.
Page
Write
If this bit is
written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Zpointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM
instruction is executed within four clock cycles. The CPU is halted during the
entire Page Write operation if the NRWW section is addressed.
Page
Erase
If this bit is
written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon
completion of a Page Erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write operation if the NRWW section
is addressed.
Store Program
Memory
This bit enables the
SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a
special meaning, see description above. If only SPMEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by
the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear
upon completion of an SPM instruction, or if no SPM instruction is executed within
four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high
until the operation is completed.
Writing any other combination than
“10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have
no effect.