TIMSK – Timer/Counter Interrupt Mask Register

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

Name:
TIMSK
Offset:
0x39 [ID-00000312]
Reset:
0
Access:
When addressing I/O registers as data space the offset address is 0x59
Bit76543210
TOIE0
AccessR/W
Reset0

Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable.

Timer/Counter0 Overflow Interrupt Enable.

When the TOIE0 bit is written to one, and the I-bit in the STATUS Register is set (one), the Timer/Counter0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, for example when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).