TIFR – Timer/Counter Interrupt Flag Register

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.

Name:
TIFR
Offset:
0x38 [ID-000004b0]
Reset:
0
Access:
When addressing I/O Registers as data space the offset address is 0x58
Bit76543210
TOV0
AccessR/W
Reset0

Bit 0 – TOV0: Timer/Counter0 Overflow Flag

Timer/Counter

0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.