Control C - Async Mode

This register description is valid for all modes except Master SPI mode. When the USART Communication mode bits (CMODE) in this register are written to 'MSPI', see Control C - Master SPI Mode for the correct description.

Name:
CTRLC
Offset:
0x07
Reset:
0x03
Access:
-
Bit76543210
CMODE[1:0]PMODE[1:0]SBMODECHSIZE[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000011

Bits 7:6 – CMODE[1:0]: USART Communication Mode

USART Communication Mode

Writing these bits select the Communication mode of the USART.

Writing a 0x3 to these bits alters the available bit fields in this register, see Control C - Master SPI Mode.

ValueNameDescription
0x0 ASYNCHRONOUS Asynchronous USART
0x1 SYNCHRONOUS Synchronous USART
0x2 IRCOM Infrared Communication
0x3 MSPI Master SPI

Bits 5:4 – PMODE[1:0]: Parity Mode

Parity Mode

Writing these bits enable and select the type of parity generation.

When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data, compare it to the PMODE setting, and set the Parity Error flag (PERR) in the STATUS register (USARTn.STATUS) if a mismatch is detected.

ValueNameDescription
0x0 DISABLED Disabled
0x1 - Reserved
0x2 EVEN Enabled, Even Parity
0x3 ODD Enabled, Odd Parity

Bit 3 – SBMODE: Stop Bit Mode

Stop Bit Mode

Writing this bit selects the number of Stop bits to be inserted by the transmitter.

The receiver ignores this setting.

ValueDescription
0 1 Stop bit
1 2 Stop bits

Bits 2:0 – CHSIZE[2:0]: Character Size

Character Size

Writing these bits select the number of data bits in a frame. The receiver and transmitter use the same setting. For 9BIT character size, the order of which byte to read or write first, low or high byte of RXDATA or TXDATA is selectable.
ValueNameDescription
0x0 5BIT 5-bit
0x1 6BIT 6-bit
0x2 7BIT 7-bit
0x3 8BIT 8-bit
0x4 - Reserved
0x5 - Reserved
0x6 9BITL 9-bit (Low byte first)
0x7 9BITH 9-bit (High byte first)