Synchronous Slave External Clock limitations

An External clock (XCK) is used in Synchronous Slave mode operation. The XCK clock input is sampled on the peripheral clock frequency and the maximum XCK clock frequency (fXCK) is limited by the following:

The USART will perform clock recovery on the external clock (XCK) signal when configured in Synchronous Slave mode, configuring the BAUD register will therefore have no impact on the transfer speed. The XCK signal must be sampled twice for each rising and falling edge to achieve successful clock recovery. The maximum XCK speed in Synchronous operation mode is therefore limited by the following:

fslave_XCK<fCLK_PER4

If the XCK clock has jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK clock speed must be reduced accordingly to ensure that XCK is sampled a minimum of 2 times for each edge.