Control C
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPDSEL | CMPCSEL | FIFTY | AUPDATE | CMPOVR | |||
AccessR/W | R/W | R/W | R/W | R/W | |||
Reset0 | 0 | 0 | 0 | 0 |
Compare D Output Select
Value | Name | Description |
---|---|---|
0 | PWMA | Waveform A |
1 | PWMB | Waveform B |
Compare C Output Select
Value | Name | Description |
---|---|---|
0 | PWMA | Waveform A |
1 | PWMB | Waveform B |
Fifty Percent Waveform
If the two waveforms have identical characteristics, this bit can be written to ‘1’. This will cause any values written to register TCDn.CMPBSET/TCDn.CLR also to be written to the register TCDn.CMPASET/TCDn.CLR.
Automatically Update
If this bit is written to ‘1’ a synchronization at the end of the TCD cycle is automatically requested after the Compare B Clear High register (TCDn.CMPBCLRH) is written.
If the fifty percent waveform is enabled by setting the FIFTY bit in this register, writing the Compare A Clear High register will also request a synchronization at the end of the TCD cycle if the AUPDATE bit is set.
Compare Output Value Override
When this bit is written to ‘1’, default values of the Waveform Outputs A and B are overridden by the values written in the Compare x Value in active state bit fields in the Control D register (CMPnxVAL bit in TCDn.CTRLD). See the Control D register description for more details.