Dither Value
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DITHER[3:0] | |||||||
Access | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 |
Dither Value
These bits configure the fractional adjustment of the on-time or off-time according to Dither Selection bits (DITHERSEL) in the Dither Control register (TCDn.DITCTRL). The DITHER value is added to a 4-bit accumulator at the end of each TCD cycle. When the accumulator overflows the frequency adjustment will occur.
The DITHER bits are double-buffered so the new value is copied in at an update condition.