Interrupt Flags

Name:
INTFLAGS
Offset:
0x03
Reset:
0x00
Access:
-
Bit76543210
RXCIF/IFTXCIF/WRCOLDREIFSSIFBUFOVF
AccessR/WR/WR/WR/WR/W
Reset00000

Bit 7 – RXCIF/IF: Receive Complete Interrupt Flag/Interrupt Flag

Receive Complete Interrupt Flag/Interrupt Flag

RXCIF: In Buffer mode, this flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). In the Non-Buffer mode, this bit does not have any effect.

When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from SPIn.DATA in order to clear RXCIF. If not, a new interrupt will occur directly after the return from the current interrupt. This flag can also be cleared by writing a '1' to its bit location.

IF: This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the SPIn.DATA register. If SS is configured as input and is driven low when the SPI is in Master mode, this will also set this flag. IF is cleared by hardware when executing the corresponding interrupt vector. Alternatively, the IF flag can be cleared by first reading the SPIn.INTFLAGS register when IF is set, and then accessing the SPIn.DATA register.

Bit 6 – TXCIF/WRCOL: Transfer Complete Interrupt Flag/Write Collision Flag

Transfer Complete Interrupt Flag/Write Collision Flag

TXCIF: In Buffer mode, this flag is set when all the data in the transmit shift register has been shifted out and there is no new data in the transmit buffer (SPIn.DATA). The flag is cleared by writing a ‘1’ to its bit location. In the Non-Buffer mode, this bit does not have any effect.

WRCOL: The WRCOL flag is set if the SPIn.DATA register is written to before a complete byte has been shifted out. This flag is cleared by first reading the SPIn.INTFLAGS register when WRCOL is set, and then accessing the SPIn.DATA register.

Bit 5 – DREIF: Data Register Empty Interrupt Flag

Data Register Empty Interrupt Flag

In Buffer mode, this flag indicates whether the transmit buffer (SPIn.DATA) is ready to receive new data. The flag is ‘1’ when the transmit buffer is empty and ‘0’ when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift register. DREIF is set to ‘0’ after a reset to indicate that the transmitter is ready. In the Non-Buffer mode, this bit is always ‘0’.

DREIF is cleared by writing SPIn.DATA. When interrupt-driven data transmission is used, the software must either write new data to SPIn.DATA in order to clear DREIF or disable the Data register empty interrupt. If not, a new interrupt will occur directly after the return from the current interrupt.

Bit 4 – SSIF: Slave Select Trigger Interrupt Flag

Slave Select Trigger Interrupt Flag

In Buffer mode, this flag indicates that the SPI has been in Master mode and the SS line has been pulled low externally so the SPI is now working in Slave mode. The flag will only be set if the Slave Select Disable bit (SSD) is not ‘1’. The flag is cleared by writing a ‘1’ to its bit location. In the Non-Buffer mode, this bit is always ‘0’.

Bit 0 – BUFOVF: Buffer Overflow

Buffer Overflow

This flag is only used in Buffer mode. This flag indicates data loss due to a receiver buffer full condition. This flag is set if a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full (two characters) and a third byte has been received in the Shift register. If there is no transmit data the buffer overflow will not be set before the start of a new serial transfer. This flag is valid until the receive buffer (SPIn.DATA) is read. Always write this bit location to ‘0’ when writing the SPIn.INTFLAGS register. In the Non-Buffer mode, this bit is always ‘0’.