ADACQ

ADC Acquisition Time Control Register
Name:
ADACQ
Offset:
0xF5C
Reset:
Access:
Bit76543210
ADACQ[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 7:0 – ADACQ[7:0]: Acquisition (charge share time) Select bits

Acquisition (charge share time) Select bits

ValueDescription
0x01 to 0xFF Number of ADC clock periods in the acquisition time
0x00 Acquisition time is not included in the data conversion cycle