TMR0
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TMR0H[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMR0L[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TMR0 Most Significant Counter bits
Value | Name | Description |
---|---|---|
0 to 255 | T016BIT = 0 |
8-bit Timer 0 Period Value. TMR0L continues counting from 0 when this value is reached. |
0 to 255 | T016BIT = 1 |
16-bit Timer 0 Most Significant Byte |