NVMCON1 and NVMCON2 Registers

Access to the data EEPROM is controlled by two registers: NVMCON1 and NVMCON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM.

The NVMCON2 register is not a physical register. It is used exclusively in the memory write and erase unlock sequences. Reading NVMCON2 will read all ‘0’s.

The NVMCON1 register is the control register for data and program memory access. Control bits NVMREG determine if the access will be to program, Data EEPROM Memory or the User IDs, Configuration bits, Revision ID and Device ID.

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear.

Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation.

The WR control bit initiates write operations. The bit can be set but not cleared by software. It is cleared only by hardware at the completion of the write operation.

The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete.

The NVMIF interrupt flag bit of the PIRx register is set when the write is complete. It must be cleared by software.

The RD bit cannot be set when accessing program memory (NVMREG = 0b10). Program memory is read using table read instructions. See Table Read Operations regarding table reads.