CLKRCON
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN | DC[1:0] | DIV[2:0] | |||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | ||
Reset0 | 1 | 0 | 0 | 0 | 0 |
Value | Description |
---|---|
1 |
Reference clock module enabled |
0 |
Reference clock module is disabled |
Value | Description |
---|---|
11 |
Clock outputs duty cycle of 75% |
10 |
Clock outputs duty cycle of 50% |
01 |
Clock outputs duty cycle of 25% |
00 |
Clock outputs duty cycle of 0% |
Value | Description |
---|---|
111 |
Base clock value divided by 128 |
110 |
Base clock value divided by 64 |
101 |
Base clock value divided by 32 |
100 |
Base clock value divided by 16 |
011 |
Base clock value divided by 8 |
010 |
Base clock value divided by 4 |
001 |
Base clock value divided by 2 |
000 |
Base clock value |