PIE0

Peripheral Interrupt Enable Register 0
Note:
  1. 1.PIR0 interrupts are not disabled by the PEIE bit in the INTCON register.
Name:
PIE0
Offset:
0xE29
Reset:
Access:
Bit76543210
TMR0IEIOCIEINT3 IEINT2IEINT1IEINT 0IE
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bit 5 – TMR0IE: Timer0 Interrupt Enable bit(1)

Timer0 Interrupt Enable bit(1)

ValueDescription
1 Enabled
0 Disabled

Bit 4 – IOCIE: Interrupt-on-Change Enable bit(1)

Interrupt-on-Change Enable bit(1)

ValueDescription
1 Enabled
0 Disabled

Bits 0, 1, 2, 3 – INTxIE: External Interrupt ‘x’ Enable bit(1)

External Interrupt ‘x’ Enable bit(1)

ValueDescription
1 Enabled
0 Disabled