The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable the CLKR output.
When the reference clock output is disabled, the output signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the EN bit is clear.