Register Summary - EUSART

Offset Name Bit Pos.                

0x00

...

0x0EDB

Reserved                  
0x0EDC RC5REG 7:0 RCREG[7:0]
0x0EDD TX5REG 7:0 TXREG[7:0]
0x0EDE SP5BRG 7:0 SPBRGL[7:0]
15:8 SPBRGH[7:0]
0x0EE0 RC5STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0x0EE1 TX5STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0x0EE2 BAUD5CON 7:0 ABDOVF RCIDL   SCKP BRG16   WUE ABDEN
0x0EE3 RC4REG 7:0 RCREG[7:0]
0x0EE4 TX4REG 7:0 TXREG[7:0]
0x0EE5 SP4BRG 7:0 SPBRGL[7:0]
15:8 SPBRGH[7:0]
0x0EE7 RC4STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0x0EE8 TX4STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0x0EE9 BAUD4CON 7:0 ABDOVF RCIDL   SCKP BRG16   WUE ABDEN
0x0EEA RC3REG 7:0 RCREG[7:0]
0x0EEB TX3REG 7:0 TXREG[7:0]
0x0EEC SP3BRG 7:0 SPBRGL[7:0]
15:8 SPBRGH[7:0]
0x0EEE RC3STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0x0EEF TX3STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0x0EF0 BAUD3CON 7:0 ABDOVF RCIDL   SCKP BRG16   WUE ABDEN
0x0EF1 RC2REG 7:0 RCREG[7:0]
0x0EF2 TX2REG 7:0 TXREG[7:0]
0x0EF3 SP2BRG 7:0 SPBRGL[7:0]
15:8 SPBRGH[7:0]
0x0EF5 RC2STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0x0EF6 TX2STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0x0EF7 BAUD2CON 7:0 ABDOVF RCIDL   SCKP BRG16   WUE ABDEN

0x0EF8

...

0x0F97

Reserved                  
0x0F98 RC1REG 7:0 RCREG[7:0]
0x0F99 TX1REG 7:0 TXREG[7:0]
0x0F9A SP1BRG 7:0 SPBRGL[7:0]
15:8 SPBRGH[7:0]
0x0F9C RC1STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0x0F9D TX1STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0x0F9E BAUD1CON 7:0 ABDOVF RCIDL   SCKP BRG16   WUE ABDEN