SAMPCTRL

Sampling Time Control

Name:: SAMPCTRL
Offset:: 0x0D [ID-0000120e]
Reset:: 0x00
Access:: PAC Write-Protection, Write-Synchronized

Bit7	6	5	4	3	2	1	0
OFFCOMP		SAMPLEN[5:0]
AccessR/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset0		0	0	0	0	0	0

Bit 7 – OFFCOMP: Comparator Offset Compensation Enable

Comparator Offset Compensation Enable

Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift. This compensation increases the sampling time by three clock cycles.

This bit must be set to zero to validate the SAMPLEN value. It’s not possible to use OFFCOMP=1 and SAMPLEN>0.

Bits 5:0 – SAMPLEN[5:0]: Sampling Time Length

Sampling Time Length

These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation:

Sampling time=SAMPLEN+1⋅CLKADC