Next Descriptor Address
Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DESCADDR[31:24] | |||||||
Access | |||||||
Reset | |||||||
Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DESCADDR[23:16] | |||||||
Access | |||||||
Reset | |||||||
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DESCADDR[15:8] | |||||||
Access | |||||||
Reset | |||||||
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DESCADDR[7:0] | |||||||
Access | |||||||
Reset |
Next Descriptor Address
This bit group holds the LP SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this LP SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor.