Next Descriptor Address

The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name:
DESCADDR
Offset:
0x0C [ID-00001ece]
Reset:
-
Access:
-
Bit3130292827262524
DESCADDR[31:24]
Access
Reset
Bit2322212019181716
DESCADDR[23:16]
Access
Reset
Bit15141312111098
DESCADDR[15:8]
Access
Reset
Bit76543210
DESCADDR[7:0]
Access
Reset

Bits 31:0 – DESCADDR[31:0]: Next Descriptor Address

Next Descriptor Address

This bit group holds the LP SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this LP SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor.