Host Interrupt Pipe Set Register

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.

This register is cleared by USB reset or when PEN[n] is zero.

Name:
PINTENSET
Offset:
0x109 + (n x 0x20) [ID-0000306e]
Reset:
0x0000
Access:
PAC Write-Protection
Bit76543210
STALLTXSTPPERRTRFAILTRCPT1TRCPT0
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bit 5 – STALL: Stall Interrupt Enable

Stall Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Stall interrupt.

ValueDescription
0 The Stall interrupt is disabled.
1 The Stall interrupt is enabled.

Bit 4 – TXSTP: Transmitted Setup Interrupt Enable

Transmitted Setup Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transmitted Setup interrupt.

ValueDescription
0 The Transmitted Setup interrupt is disabled.
1 The Transmitted Setup interrupt is enabled.

Bit 3 – PERR: Pipe Error Interrupt Enable

Pipe Error Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Pipe Error interrupt.

ValueDescription
0 The Pipe Error interrupt is disabled.
1 The Pipe Error interrupt is enabled.

Bit 2 – TRFAIL: Transfer Fail Interrupt Enable

Transfer Fail Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Fail interrupt.

ValueDescription
0 The Transfer Fail interrupt is disabled.
1 The Transfer Fail interrupt is enabled.

Bit 1 – TRCPT1: Transfer Complete 1 interrupt Enable

Transfer Complete 1 interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 1.

ValueDescription
0 The Transfer Complete 1 interrupt is disabled.
1 The Transfer Complete 1 interrupt is enabled.

Bit 0 – TRCPT0: Transfer Complete 0 interrupt Enable

Transfer Complete 0 interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 0.

0.2.7 Host Registers - Pipe RAM

ValueDescription
0 The Transfer Complete 0 interrupt is disabled.
1 The Transfer Complete 0 interrupt is enabled.