In master mode, a single SS chip select can be controlled by hardware by writing the Master Slave Select Enable (CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames.
In SSHardware Controlled, the time T is between one and two baud cycles depending on the SPI transfer mode.
Figure 1. Hardware Controlled SS
When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.