Device Status Bank
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ERROFLOW | CRCERR | ||||||
| Access | R/W | R/W | |||||
| Reset | x | x |
Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
| Value | Description |
|---|---|
| 0 | No Error Flow detected. |
| 1 | A Error Flow has been detected. |
CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
0.2.5 Host Registers - Common
| Value | Description |
|---|---|
| 0 | No CRC Error. |
| 1 | CRC Error detected. |