Synchronization Busy
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE | SWRST | ||||||
Access | R | R | |||||
Reset | 0 | 0 |
Synchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Synchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.