Synchronization Busy

Name:
SYNCBUSY
Offset:
0x02 [ID-0000306e]
Reset:
0x0000
Access:
-
Bit76543210
ENABLESWRST
AccessRR
Reset00

Bit 1 – ENABLE: Synchronization Enable status bit

Synchronization Enable status bit

This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.

This bit is set when the synchronization of ENABLE register between clock domains is started.

Bit 0 – SWRST: Synchronization Software Reset status bit

Synchronization Software Reset status bit

This bit is cleared when the synchronization of SWRST register between the clock domains is complete.

This bit is set when the synchronization of SWRST register between clock domains is started.