DAC0 Control

Name:
DACCTRL0
Offset:
0x0C [ID-00000bc7]
Reset:
0x0000
Access:
PAC Write-Protection, Enabled-Protected
Bit15141312111098
REFRESH[3:0]
AccessR/WR/WR/WR/W
Reset0000
Bit76543210
DITHERRUNSTDBYCCTRL[1:0]ENABLELEFTADJ
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bits 11:8 – REFRESH[3:0]: Refresh period

Refresh period

This field defines the refresh period.
ValueDescription
0x0 Refresh is disabled.
0x1 Reserved
0x2 to 0xF TREFRESH=REFRESH×30.52μs

Bit 7 – DITHER: Dithering Mode

Dithering Mode

ValueDescription
0 Dithering mode is disabled.
1 Dithering mode is enabled.

Bit 6 – RUNSTDBY: Run in Standby

Run in Standby

This bit controls the behavior of DAC0 during standby sleep mode.

ValueDescription
0 DAC0 is disabled during standby sleep mode.
1 DAC0 continues to operate during standby sleep mode.

Bits 3:2 – CCTRL[1:0]: Current Control

Current Control

This field defines the current in output buffer according to conversion rate.

Figure 1. Current Control
ValueNameDescription
0x0 CC100K GCLK_DAC ≤ 1.2MHz (100kSPS)
0x1 CC1M 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS)
0x2 CC12M 6MHz < GCLK_DAC ≤ 12MHz (1MSPS)
0x3 Reserved

Bit 1 – ENABLE: Enable DAC0

Enable DAC0

This bit enables DAC0 when DAC Controller is enabled (CTRLA.ENABLE).

ValueDescription
0 DAC0 is disabled.
1 DAC0 is enabled.

Bit 0 – LEFTADJ: Left Adjusted Data

Left Adjusted Data

This bit controls how the 12-bit conversion data is adjusted in the Data and Data Buffer registers.

ValueDescription
0 DATA0 and DATABUF0 registers are right-adjusted.
1 DATA0 and DATABUF0 registers are left-adjusted.