A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.
Mode | Mode Entry | Wake-Up Sources |
---|---|---|
IDLE | SLEEPCFG.SLEEPMODE = IDLE | Synchronous (2) (APB, AHB), asynchronous (1) |
STANDBY | SLEEPCFG.SLEEPMODE = STANDBY | Synchronous(3), Asynchronous |
BACKUP | SLEEPCFG.SLEEPMODE = BACKUP | Backup reset detected by the RSTC |
OFF | SLEEPCFG.SLEEPMODE = OFF | External Reset |
The sleep modes (idle, standby, backup, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Refer to Power Domain Controller for the power domain gating effect.
Mode | Main clock | CPU | AHBx and APBx clock | GCLK clocks | Oscillators | Regulator | NVM | |
---|---|---|---|---|---|---|---|---|
ONDEMAND = 0 | ONDEMAND = 1 | |||||||
Active | Run | Run | Run | Run(3) | Run | Run if requested | MAINVREG | active |
IDLE | Run | Stop | Stop(1) | Run(3) | Run | Run if requested | MAINVREG | active |
STANDBY | Stop(1) | Stop | Stop(1) | Stop(1) | Run if requested or RUNSTDBY=1 | Run if requested | MAINVREG in low power mode | Ultra Low power |
BACKUP | Stop | Stop | Stop | Stop | Stop | Stop | Backup regulator (ULPVREG) | OFF |
OFF | Stop | Stop | Stop | OFF | OFF | OFF | OFF | OFF |