DPLL Status

Name:
DPLLSTATUS
Offset:
0x3C [ID-00001eee]
Reset:
0x00
Access:
–
Bit76543210
CLKRDYLOCK
AccessRR
Reset00

Bit 1 – CLKRDY: Output Clock Ready

Output Clock Ready

ValueDescription
0 The DPLL output clock is off.
1 The DPLL output clock in on.

Bit 0 – LOCK: DPLL Lock status bit

DPLL Lock status bit

ValueDescription
0 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the target frequency.
1 The DPLL Lock signal is asserted when the desired frequency is reached.