Interrupt Enable Set
Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EVDn[11:8] | |||||||
Access | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | |||
Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EVDn[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OVRn[11:8] | |||||||
Access | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | |||
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVRn[7:0] | |||||||
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Event Detected Channel n Interrupt Enable [n = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt.
Value | Description |
---|---|
0 | The Event Detected Channel n interrupt is disabled. |
1 | The Event Detected Channel n interrupt is enabled. |
Overrun Channel n Interrupt Enable [n = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt.
Value | Description |
---|---|
0 | The Overrun Channel n interrupt is disabled. |
1 | The Overrun Channel n interrupt is enabled. |