Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x14 [ID-0000120d]
Reset:
0x00000000
Access:
PAC Write-Protection
Bit3130292827262524
EVDn[11:8]
AccessR/WR/WR/WR/W
Reset0000
Bit2322212019181716
EVDn[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit15141312111098
OVRn[11:8]
AccessR/WR/WR/WR/W
Reset0000
Bit76543210
OVRn[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 27:16 – EVDn: Event Detected Channel n Interrupt Enable [n = 11..0]

Event Detected Channel n Interrupt Enable [n = 11..0]

Writing '0' to this bit has no effect.


Writing '1' to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt.

ValueDescription
0 The Event Detected Channel n interrupt is disabled.
1 The Event Detected Channel n interrupt is enabled.

Bits 11:0 – OVRn: Overrun Channel n Interrupt Enable [n = 11..0]

Overrun Channel n Interrupt Enable [n = 11..0]

Writing '0' to this bit has no effect.


Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt.

ValueDescription
0 The Overrun Channel n interrupt is disabled.
1 The Overrun Channel n interrupt is enabled.