Quality of Service Control
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DQOS[1:0] | FQOS[1:0] | WRBQOS[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 1 | 0 | |
Data Transfer Quality of Service
These bits define the memory priority access during the data transfer operation.
| DQOS[1:0] | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
Fetch Quality of Service
These bits define the memory priority access during the fetch operation.
| FQOS[1:0] | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
Write-Back Quality of Service
These bits define the memory priority access during the write-back operation.
| WRBQOS[1:0] | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |