INTFLAG

Bit31	30	29	28	27	26	25	24

Access
Reset
Bit23	22	21	20	19	18	17	16
				DPLLLDRTO	DPLLLTO	DPLLLCKF	DPLLLCKR
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0
Bit15	14	13	12	11	10	9	8
			DFLLRCS	DFLLLCKC	DFLLLCKF	DFLLOOB	DFLLRDY
Access			R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0
Bit7	6	5	4	3	2	1	0
			OSC16MRDY				XOSCRDY
Access			R/W				R/W
Reset			0				0

Bit 19 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete

DPLL Loop Divider Ratio Update Complete

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag.

Bit 18 – DPLLLTO: DPLL Lock Timeout

DPLL Lock Timeout

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag.

Bit 17 – DPLLLCKF: DPLL Lock Fall

DPLL Lock Fall

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Fall interrupt flag.

Bit 16 – DPLLLCKR: DPLL Lock Rise

DPLL Lock Rise

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DPLL Lock Rise interrupt flag.

Bit 12 – DFLLRCS: DFLL Reference Clock Stopped

DFLL Reference Clock Stopped

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag.

Bit 11 – DFLLLCKC: DFLL Lock Coarse

DFLL Lock Coarse

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DFLL Lock Coarse bit in the Status register (STATUS.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DFLL Lock Coarse interrupt flag.

Bit 10 – DFLLLCKF: DFLL Lock Fine

DFLL Lock Fine

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DFLL Lock Fine bit in the Status register (STATUS.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DFLL Lock Fine interrupt flag.

Bit 9 – DFLLOOB: DFLL Out Of Bounds

DFLL Out Of Bounds

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DFLL Out Of Bounds bit in the Status register (STATUS.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DFLL Out Of Bounds interrupt flag.

Bit 8 – DFLLRDY: DFLL Ready

DFLL Ready

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the DFLL Ready bit in the Status register (STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the DFLL Ready interrupt flag.

Bit 4 – OSC16MRDY: OSC16M Ready

OSC16M Ready

This flag is cleared by writing '1' to it.

This flag is set on 0-to-1 transition of the OSC16M Ready bit in the Status register (STATUS.OSC16MRDY) and will generate an interrupt request if INTENSET.OSC16MRDY is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the OSC16M Ready interrupt flag.

Bit 0 – XOSCRDY: XOSC Ready

XOSC Ready

This flag is cleared by writing '1' to it.

This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'.

Writing '0' to this bit has no effect.

Writing '1' to this bit clears the XOSC Ready interrupt flag.