Control

The I/O pins are assembled in PORT groups with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each PORT group has its own set of PORT registers with offset 0x80. The available number of PORT groups may depend on the package/pin number of the device.

Name:
CTRL
Offset:
0x24 [ID-000011ca]
Reset:
0x00000000
Access:
PAC Write-Protection
Bit3130292827262524
SAMPLING[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit2322212019181716
SAMPLING[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit15141312111098
SAMPLING[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit76543210
SAMPLING[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 31:0 – SAMPLING[31:0]: Input Sampling Mode

Input Sampling Mode

Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR).

The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.

ValueDescription
0 The I/O pin input synchronizer is disabled.
1 The I/O pin input synchronizer is enabled.