Data Output Value Clear

This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers.

The I/O pins are assembled in PORT groups with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each PORT group has its own set of PORT registers with offset 0x80. The available number of PORT groups may depend on the package/pin number of the device.

Name:
OUTCLR
Offset:
0x14 [ID-000011ca]
Reset:
0x00000000
Access:
PAC Write-Protection
Bit3130292827262524
OUTCLR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit2322212019181716
OUTCLR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit15141312111098
OUTCLR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit76543210
OUTCLR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 31:0 – OUTCLR[31:0]: PORT Data Output Value Clear

PORT Data Output Value Clear

Writing '0' to a bit has no effect.

Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the Data Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an internal pull-down.
ValueDescription
0

The corresponding I/O pin in the PORT group will keep its configuration.

1

The corresponding I/O pin output is driven low, or the input is connected to an internal pull-down.