Register Summary

Offset	Name	Bit Pos.
0x00	CTRLA	7:0								SWRST
0x01 ... 0x03	Reserved
0x04	SYNCBUSY	7:0	GENCTRLx	GENCTRLx	GENCTRLx	GENCTRLx	GENCTRLx	GENCTRLx		SWRST
		15:8						GENCTRLx	GENCTRLx	GENCTRLx
		23:16
		31:24
0x08 ... 0x1F	Reserved
0x20	GENCTRLn0	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x24	GENCTRLn1	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x28	GENCTRLn2	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x2C	GENCTRLn3	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x30	GENCTRLn4	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x34	GENCTRLn5	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x38	GENCTRLn6	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x3C	GENCTRLn7	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x40	GENCTRLn8	7:0				SRC[4:0]
		15:8			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
		23:16	DIV[7:0]
		31:24	DIV[15:8]
0x44 ... 0x7F	Reserved
0x80	PCHCTRL0	7:0	WRTLOCK	CHEN			GEN[3:0]
		15:8
		23:16
		31:24
...
0x0108	PCHCTRL34	7:0	WRTLOCK	CHEN			GEN[3:0]
		15:8
		23:16
		31:24